STM32U5A5QJ datasheet(49/382 Pages) STMICROELECTRONICS

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DS13543 Rev 1

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STM32U5Axxx

Functional overview

Some of the PWR configuration bits security is defined by the security of other peripherals:

•

The VOS (voltage scaling) configuration is secure when the system clock selection is

secure in RCC.

•

The I/O pull-up/pull-down in Standby mode configuration is secure when the

corresponding GPIO is secure.

3.10

Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous

communication between them and support the saving of CPU resources (thus power supply

consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep,

Low-power Run and Sleep, Stop 0, Stop 1 and Stop 2 modes.

3.11

Reset and clock controller (RCC)

The RCC manages the different reset types, and generates all clocks for the bus and

peripherals.

The RCC distributes the clocks coming from the different oscillators to the core and to

the peripherals. It also manages the clock gating for low-power modes and ensures the

clock robustness. It features:

•

Clock prescaler: in order to get the best trade-off between speed and current

consumption, the clock frequency to the CPU and peripherals can be adjusted by

a programmable prescaler.

•

Clock security system: clock sources can be changed safely on-the-fly in Run mode

through a configuration register.

•

Clock management: in order to reduce the power consumption, the clock controller

can stop the clock to the core, individual peripherals or memory.

•

System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

–

HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can

supply a PLL. The HSE can also be configured in bypass mode for an external

clock.

–

HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that can

supply a PLL.

–

MSI (multispeed internal RC oscillator) trimmable by software, that can generate

16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is

available in the system (LSE), the MSI frequency can be automatically trimmed by

hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.

–

System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency

at 160 MHz.

•

HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be

used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output

on the MCO.

•

UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be

enabled prior to the UCPD kernel clock use.

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