STM32U5A5QJ datasheet(97/382 Pages) STMICROELECTRONICS

97 / 382 page

DS13543 Rev 1

97/382

STM32U5Axxx

Functional overview

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Configurable transmit Event FIFO

•

Programmable loop-back test mode

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Maskable module interrupts

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Two clock domains: APB bus interface and CAN core kernel clock

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Power-down support

3.55

USB on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed device/host/OTG peripheral with integrated

transceivers. The OTG_HS peripheral is compliant with the USB 2.0 specification and with

the OTG 2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume.

This interface requires a precise 60 MHz clock that is generated from the internal

USB PHY PLL (the clock source must use a HSE crystal oscillator).

The OTG_HS features are:

•

USB-IF certified to the Universal Serial Bus Specification Rev 2.0

•

On-chip high-speed PHY

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Full support (PHY) for the optional OTG (on-the-go) protocol detailed in the OTG

Supplement Rev 2.0 specification

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Integrated support for A-B device identification (ID line)

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Supports OTG monitoring of VBUS levels with internal comparators

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Supports dynamic host-peripheral switch of role

•

Software-configurable to operate as USB on-the-go high-speed dual role device

•

Supports HS/FS SOF and LS keep-alives with

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SOF pulse PAD connectivity

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SOF pulse internal connection to timer (TIMx)

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Configurable framing period

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Configurable end of frame interrupt

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USB 2.0 link power management (LPM) support

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Internal DMA with thresholding support and software selectable AHB burst type in DMA

mode

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Power saving features such as system stop during USB suspend, switch-off of clock

domains internal to the digital core, PHY and DFIFO power management

•

Dedicated RAM of 4 Kbytes with advanced FIFO control:

–

Configurable partitioning of RAM space into different FIFOs for flexible and

efficient use of RAM

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Each FIFO able to hold multiple packets

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Dynamic memory allocation

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Configurable FIFO sizes that are not powers of two to allow the use of contiguous

memory locations

•

Max guaranteed USB bandwidth for up to one frame (1 ms) without system intervention

•

Support of charging port detection as described in Battery Charging Specification

revision 1.2

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