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STM32U5A5QJ Datasheet(PDF) 91 Page - STMicroelectronics |
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STM32U5A5QJ Datasheet(HTML) 91 Page - STMicroelectronics |
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91 / 382 page  DS13543 Rev 1 91/382 STM32U5Axxx Functional overview 99 • Two internal FIFOs for transmit and receive data Each FIFO can be enabled/disabled by software and come with a status flag. • A common programmable transmit and receive baud rate • Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK • Auto baud rate detection • Programmable data word length (7, 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Synchronous Master/Slave mode and clock output/input for synchronous communications • SPI slave transmission underrun error flag • Single-wire half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Interrupt sources with flags • Multiprocessor communications: wake-up from Mute mode by idle line detection or address mark detection • Autonomous functionality in Stop mode with wake-up from stop capability • LIN master synchronous break send capability and LIN slave break detection capability – 13-bit break generation and 10/11-bit break detection when USART is hardware configured for LIN • IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode • Smartcard mode – Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in the ISO/IEC 7816-3 standard – 0.5 and 1.5 stop bits for Smartcard operation • Support for Modbus communication – Timeout feature – CR/LF character recognition 3.50.2 Low-power universal asynchronous receiver transmitter (LPUART) The LPUART supports bidirectional asynchronous serial communication with minimum power consumption. It also supports half-duplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. |
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