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STM32U5A5QJ Datasheet(PDF) 38 Page - STMicroelectronics |
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STM32U5A5QJ Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 382 page ![]() Functional overview STM32U5Axxx 38/382 DS13543 Rev 1 Figure 3. STM32U5Axxx power supply overview (without SMPS) In this document, VDDIOx (with x = 1 or 2) refers to the I/O power supply. VDDIO1 is supplied by VDD. VDDIO2 is the independent power supply for PG[15:2]. During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. • During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. MSv66058V1 Core SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 Digital peripherals LSE crystal 32kHz oscillator LSI 32 kHz oscillator Backup registers RCC_BDCR and PWR_BDCR1 registers RTC TAMP BKPSRAM VDDA domain Backup domain Standby circuitry (Wakeup logic, IWDG) Low-voltage detector I/O ring VCORE domain Temperature sensor Reset block 3 x PLL Internal RC oscillators Flash memory VDDUSB VDDIO2 VDDIO1 I/O ring PG[15:2] VDDIO2 VDDA VSSA VDD11USB (1) VSS VDDIO2 domain VDD domain VCORE VSS VDD VBAT VCAP A/D converters Comparators D/A converters Operational amplifiers Voltage reference buffer USB transceiver VSS Note: 1. Only available on specific packages. LDO regulator |
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