APEX20K datasheet(9/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Functional

Description

APEX 20K devices incorporate LUT-based logic, product-term-based

logic, and memory into one device. Signal interconnections within

APEX 20K devices (as well as to and from device pins) are provided by the

FastTrack® Interconnect—a series of fast, continuous row and column

channels that run the entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/O buffer and a register that can be used as either an input

or output register to feed input, output, or bidirectional signals. When

used with a dedicated clock pin, these registers provide exceptional

performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,

66-MHz PCI compliance; JTAG BST support; slew-rate control; and

tri-state buffers. APEX 20KE devices offer enhanced I/O support,

including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,

3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V

AGP I/O standards.

The ESB can implement a variety of memory functions, including CAM,

RAM, dual-port RAM, ROM, and FIFO functions. Embedding the

memory directly into the die improves performance and reduces die area

compared to distributed-RAM implementations. Moreover, the

abundance of cascadable ESBs ensures that the APEX 20K device can

implement multiple wide memory blocks for high-density designs. The

ESB’s high speed ensures it can implement small memory blocks without

any speed penalty. The abundance of ESBs ensures that designers can

create as many different-sized memory blocks as the system requires.

Figure 1 shows an overview of the APEX 20K device.

Figure 1. APEX 20K Device Block Diagram

LUT

Memory

IOE

LUT

Memory

IOE

Product Term

LUT

Memory

IOE

Product Term

FastTrack

Interconnect

Clock Management Circuitry

IOEs support

PCI, GTL+,

SSTL-3, LVDS,

and other

standards.

ClockLock

Four-input LUT

for data path and

DSP functions.

Product-term

integration for

high-speed

control logic and

state machines.

Flexible integration

of embedded

memory, including

CAM, RAM,

ROM, FIFO, and

other memory

functions.

APEX20K Datasheet(PDF) 9 Page - Altera Corporation

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