MP2733 datasheet(47/51 Pages) MPSIND

47 / 51 page

MP2733

– 4.5A SW CHARGER WITH I2C CONTROL, NVDC POWER PATH, USB OTG

MP2733 Rev. 1.1

www.MonolithicPower.com

5/18/2023

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

The output voltage ripple can be calculated with

Equation (5):

−



SYS

ΔV

ΔR%

8 C

(5)

To guarantee a ±0.5% system voltage accuracy,

the maximum output voltage ripple must not

exceed 0.5% (e.g. 0.1%). The maximum output

voltage ripple occurs at the minimum system

voltage and the maximum input voltage.

The output capacitance (CSYS) can be calculated

with Equation (6):

−



 

SYS

8 f

ΔR

(6)

For example, if VIN = 5V, VSYS = 3.7V, L = 1µH,

fSW = 1.35MHz, and R = 0.1%, choose a 22µF

ceramic capacitor.

Selecting the NTC Resistor

Figure 7 on page 24 shows an external resistor

divider reference circuit that limits the low-

temperature

threshold

(VCOLD)

and

high-

temperature threshold (VHOT). For a given NTC

thermistor, select the appropriate RT2 and RT1

values to set the NTC window, calculated with

Equation (7) and Equation (8), respectively:

NTC_HOT

COLD

HOT

NTC_COLD

HOT

COLD

HOT

COLD

(1-V

)-R

(1 V

)



 −

−

(7)

COLD

NTC_COLD

COLD

(1-V

) (R

R )

+

(8)

Where RNTC_HOT is the value of the NTC resistor

the

high

temperature

the

required

temperature operation range, and RNTC_COLD is

the value of the NTC resistor at the low

temperature.

RT1 and RT2 allow the high-temperature limit and

low-temperature

limit

configured

independently. With this feature, the MP2733

can operate within most NTC resistor and

temperature operation range requirements.

The RT1 and RT2 values depend on the type of

NTC resistor. For example, a 103AT thermistor

must have the following electrical characteristics:

• At 0°C, R

NTC_COLD = 27.28kΩ

• At 60°C, R

NTC_HOT = 3.02kΩ

VHOT is selected to be 34% of VNTC and VCOLD is

selected to be 72% of VNTC via the REG16h

RT1 = 11.8kΩ and RT2 = 3.06kΩ.

PCB Layout Guidelines

Proper PCB layout is critical to meet specified

noise rejection requirements and high efficiency.

For the best results, follow the guidelines below:

1. Route the power stages adjacent to their

grounds. Minimize the high-side switching

node (SW and inductor), the trace lengths in

the high-current paths, and the current-

sense resistor trace.

2. Keep the switching node short, and route it

away

from

all

small

control

signals,

especially the feedback network.

3. Place the input capacitor as close as

possible to the PMID and PGND pins.

Place the output inductor close to the IC, and

connect the output capacitor between the

inductor and PGND of the IC.

5. For high-current applications, the pins for the

power pads (IN, SW, SYS, BATT, and PGND)

should be connected to as much copper on

the board as possible. This improves thermal

performance by conducting heat away from

the IC.

6. Connect a ground plane directly to the return

of all components through via holes. It is also

recommended to put via holes inside the

PGND pads for the IC, if possible. A star

ground design approach is recommended to

keep the circuit block currents isolated (high-

power PGND and low-power, small signal

AGND) which reduces noise coupling and

ground-bounce issues. A single ground

plane for this design offers good results. With

a small layout and a single ground plane,

there is no ground-bounce, and having the

components separated minimizes coupling

between signals and stability requirements.

7. Pull the connection wire from the MCU (I2C)

far from the SW mode and copper regions.

8. Place SCL and SDA in close parallel.

MP2733 Datasheet(PDF) 47 Page - MPS Industries, Inc.

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