PCF8820 datasheet(34/60 Pages) PHILIPS

34 / 60 page

2000 Dec 07

Philips Semiconductors

Product speciﬁcation

× 101 Grey-scale/ECB colour dot matrix

LCD driver

PCF8820

12 TIMING

VDD1 = 2.5 to 5.5 V; VDD2 =VDD3 = 2.7 to 5.5 V; VSS1 =VSS2 =0V; VLCDIN = 4.5 to 14.5 V; Tamb = −40 °C to +85 °C;

unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Clock signal

fframe

LCD frame frequency

not calibrated; note 1

158

fframe(cal1)

LCD frame frequency

calibrated; accurate calibration

timing of 190

µs; note 2

fframe(cal2)

LCD frame frequency

calibrated; accurate calibration

timing of 190

µs

fosc

oscillator frequency

not calibrated; note 3

190

336

670

kHz

PAD OSC

fext

external clock frequency

not calibrated

190

336

670

kHz

Reset timing; see Fig.24

PAD RES

tWL

reset pulse width LOW

1.0

−−µs

tWH

reset pulse width HIGH

1.5

−−µs

tW(spike)

tolerable spike width on RES

input

−−

tsu

reset-LOW pulse set-up time

after power-on

VDD = 2.75 V; note 4

−−

µs

toper

end of reset to interface being

operational

−−

µs

LCD on and off timing; see Fig.25

PAD VLCDIN

tLCD(on)

external LCD turn-on time

after VDD1 turns on

−−

tLCD(off)

external LCD turn-off time

before VDD1 turns off

−−

I2C-bus timing; see Fig.26; note 5

PADS SCL and SDA

fSCL

SCL clock frequency

−

400

kHz

tLOW

SCL LOW time

1.3

−−µs

tHIGH

SCL HIGH time

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−

0.9

µs

rise time SDA and SCL

note 6

20 + 0.1 Cb

−

300

fall time SDA and SCL

note 6

20 + 0.1 Cb

−

300

capacitive load represented by

each bus line

−−

400

tSU;STA

set-up time repeated START

0.6

−−µs

tHD;STA

hold time START condition

0.6

−−µs

PCF8820 Datasheet(PDF) 34 Page - NXP Semiconductors

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