PM5313 datasheet(46/646 Pages) PMC

46 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

BLOCK DIAGRAM

DS3RICL K

DS3ROCL K [12:1]

DS3RDA T[12:1]

Rx DS-3

System

Interface

Rx T elecom b us

System

Interface

DC K

DC 1J1V1[4:1 ]

DPL [4:1]

DD [31:0]

DD P[4:1]

DF P

DPA IS

and

TPA IS

DM ODE[1:0]

Rx Pa th O/H

Processo r

(RPOP)

Microprocessor

I/F

JT AG T est

Access Port

Path Trace Buffer

(SPT B)

Rx Telecom

Aligner

(RTAL )

D S3 M apper

DROP Side

(D 3MD)

DROP Bus

PRB S

Generator/

M onitor

(DPGM )

Receive Path Processing

Slice (RPPS) #n, n= {1..12}

Serial

Control Port

Rx Ring

Control Port

(R RC P)

AC1J1V1[4:1]/AFP[4:1]

Add Bus

System

Interface

ACK

APL[4:1]

AD[31:0]

ADP[4:1]

Tx Path O/H

Processor

(TPOP)

Tx T elecom

Aligner

(TT AL)

Tx Pointer

Interpreter

(T PIP)

A DD Bus

PR BS

Generator/

Monitor

(A PGM )

D S3 M apper

A DD Side

(D3M A)

Tx DS-3

System

Interface

DS3TIC LK [12:1]

DS3TD AT [12:1]

T ransmit Path Processing

Slice (TPPS) #n, n={1..12}

OOF

Tx Line

I/F

Rx L ine

I/F

Sectio n O/H

Processor

(T SOP)

Sectio n O/H

Processor

(RSOP)

Section

Trace

Buffer

(SST B)

Line O/H

Processo r

(TL OP)

Line O/H

Processo r

(RL OP)

Tx Rin g

Control Port

Clock and

Data

Recovery

(CRSI)

Clock

Synthesis

(CSPI)

TXD+/-

TDREF0, TDREF1

TDC K

TC 1J1V 1/TF PO

TPL

PEC LV

RXD+/-

REFC LK +/-

RRCL K+/-

C0, C1

PIC L K

PIN[7:0]

FPIN

WAN

Synchroniz ation

Controller

(W ANS)

TD [7:0]

Receive APS,

Synchronization

Extractor and

Bit Error M onitor

(RASE)

TDP

TFPI

Tx Transport

Overhead

Controller

(T T OC)

Rx T ransport

Overhead

Controller

(RTOC)

ATP[1:0]

PEC L REF

PRE F EN

(BID X)

(RX_D EMUX)

(T X_REM UX)

DR OP_ T SI

ADD _T SI

RPOHC T RL

TPOHC TRL

PM ON

DROP

DL L

DLL

PM5313 Datasheet(PDF) 46 Page - PMC-Sierra, Inc

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