PM5313 datasheet(82/646 Pages) PMC

82 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

TSLD

Input

E22

The transmit section or line DCC (RSLD) bit serial

input signal contains the section data

communication channel (D1-D3) or the line data

communication channel (D4-D12) to be transmitted.

TSLD is sampled on the rising edge of TSLDCLK.

The TTOH and TTOHEN inputs take precedence

over TSLD.

The TTOC Overhead Control register contains the

TSLD_SEL register bit used to select the section or

line DCC. The same register also contains the

TX_GAPSEL register bit used to select the smooth

or gapped TSLDCLK output clock.

TLDCLK

Tristate

Output

D23

The transmit line data communication channel

(DCC) clock (TLDCLK) is used to clock in the

transmit line DCC (TLD). A smooth or gapped

version of this clock may be selected.

When selecting the smooth clock, TLDCLK is a 576

kHz clock with nominal 50% duty cycle.

When selecting the gapped clock, TLDCLK is a 576

kHz clock, with nominal 66%/33% duty cycle,

generated by gapping a 2.16 MHz clock.

In all cases, TLD is sampled on the rising edge of

TLDCLK. In gapped clock mode, a gap detector on

TLDCLK is needed to identify the MSB on TLD. An

edge detection on TFP may also be used. In

smooth clock mode, TTOHFP may be used to

identify the rising edge when the MSB should be

present on TSLD.

The TTOC Overhead Control register contains the

TX_GAPSEL register bit used to select the smooth

or gapped TLDCLK output clock and the TLD_TS

output.

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