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PM5313 Datasheet(PDF) 63 Page - PMC-Sierra, Inc |
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PM5313 Datasheet(HTML) 63 Page - PMC-Sierra, Inc |
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63 / 646 page ![]() PRODUCTION PMC-Sierra, Inc. PM5313 SPECTRA-622 DATASHEET PMC-1981162 ISSUE 6 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PROPRIETARY AND CONFIDENTIAL 31 10.3 Receive and Transmit Clocks Pin Name Type Pin No. Function RCLK Output B22 The receive clock (RCLK) output provides a timing reference for the SPECTRA-622 receive line interface outputs. RCLK is a nominally 77.76 MHz, 50% duty cycle clock. When clock recovery is enabled, RCLK is a divide by eight version of the recovered clock. When clock recovery is bypassed, RCLK is a divide by eight version of the recovered RRCLK+/- inputs. In parallel interface mode, PGMRCLK is a buffered version of the PICLK input. The RCLK output can be disabled and held low by programming the RCLKEN bit in the SPECTRA-622 Clock Control register. RFPO, SALM, LOF, LOS, OOF, LRDI and LAIS are updated on the rising edge of RCLK. RLAIS is sampled on the rising edge of RCLK. |
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