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C8051F360 Datasheet(PDF) 47 Page - Silicon Laboratories

Part # C8051F360
Description  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 Datasheet(HTML) 47 Page - Silicon Laboratories

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Rev. 1.0
47
C8051F360/1/2/3/4/5/6/7/8/9
5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)
The ADC0 subsystem for the C8051F360/1/2/6/7/8/9 consists of two analog multiplexers (referred to col-
lectively as AMUX0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion
modes, and window detector are all configurable under software control via the Special Function Registers
shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured
to measure P1.0-P3.4 (where available), the Temperature Sensor output, or VDD with respect to P1.0-
P3.4, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control reg-
ister (ADC0CN) is set to logic ‘1’. The ADC0 subsystem is in low power shutdown when this bit is logic ‘0’.
ADC0CF
10-Bit
SAR
ADC
32
ADC0CN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000
AD0BUSY (W)
VDD
ADC0LTH
23-to-1
AMUX
AD0WINT
Temp
Sensor
23-to-1
AMUX
VDD
P1.0
P1.7
001
010
011
100
CNVSTR Input
Window
Compare
Logic
P2.0
P2.7
GND
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
101
Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
AMX0P
AMX0N
P3.0
P3.4
P3.1-3.4 available on
C8051F360/1/6/8
(+)
(-)
VREF
P3.1-3.4 available on
C8051F360/1/6/8
P1.0-1.3 available on
C8051F361/2/6/7/8/9
P1.0-1.3 available on
C8051F361/2/6/7/8/9
Figure 5.1. ADC0 Functional Block Diagram



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