C8051F360 datasheet(18/288 Pages) SILABS

18 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.0

1. System Overview

C8051F36x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are

listed below. Refer to Table 1.1 for specific product feature selection.

•

High-speed pipelined 8051-compatible microcontroller core (up to 100 MIPS)

•

In-system, full-speed, non-intrusive debug interface (on-chip)

•

True 10-bit 200 ksps 16-channel single-ended/differential ADC with analog multiplexer

•

10-bit Current Output DAC

•

2-cycle 16 by 16 Multiply and Accumulate Engine

•

Precision programmable 25 MHz internal oscillator

•

Up to 32 kB of on-chip Flash memory—1024 bytes are reserved

•

1024 bytes of on-chip RAM

•

External Data Memory Interface with 64 kB address space

•

SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware

•

Four general-purpose 16-bit timers

•

Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer

function

•

On-chip Power-On Reset, VDD Monitor, and Temperature Sensor

•

Two on-chip Voltage Comparators

•

up to 39 Port I/O (5 V tolerant)

With on-chip Power-On Reset, VDD Monitor, Watchdog Timer, and clock oscillator, the C8051F36x devices

are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-cir-

cuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User soft-

ware has complete control of all peripherals, and may individually shut down any or all peripherals for

power savings.

The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip

resources), full speed, in-circuit debugging using the production MCU installed in the final application. This

debug logic supports inspection and modification of memory and registers, setting breakpoints, single

stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging

using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-

out occupying package pins.

Each device is specified for 3.0 to 3.6 V (100 MIPS) operation or 2.7 to 3.6 V (50 MIPS) operation over the

industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to

5 V. The C8051F36x devices are available in 48-pin TQFP packages, and C8051F36x devices are avail-

able in 32-pin LQFP and 28-pin QFN packages (also referred to as MLP or MLF packages). All package

types are lead-free (RoHS compliant). See Table 1.1 for ordering part numbers. Block diagrams are

included in Figure 1.1, Figure 1.2, and Figure 1.3.

C8051F360 Datasheet(PDF) 18 Page - Silicon Laboratories

C8051F360 Datasheet(HTML) 18 Page - Silicon Laboratories

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