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C8051F360 Datasheet(PDF) 86 Page - Silicon Laboratories

Part # C8051F360
Description  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 Datasheet(HTML) 86 Page - Silicon Laboratories

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C8051F360/1/2/3/4/5/6/7/8/9
86
Rev. 1.0
9.4.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 32k bytes (C8051F360/1/2/3/4/5/6/7) or 16k bytes (C8051F368/9) of internal program mem-
ory address space implemented within the CIP-51. The CIP-51 memory organization is shown in
Figure 9.2.
FLASH
(In-System
Programmable in 1024
Byte Sectors)
PROGRAM MEMORY
0x0000
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
RESERVED
0x7C00
0x7BFF
DATA MEMORY
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
C8051F360/1/2/3/4/5/6/7
FLASH
(In-System
Programmable in 1024
Byte Sectors)
0x0000
0x4000
0x3FFF
C8051F368/9
EXTERNAL DATA ADDRESS SPACE
INTERNAL DATA ADDRESS SPACE
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
0x03FF
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1024-byte boundaries
0x0400
0xFFFF
RESERVED
Figure 9.2. Memory Map
9.4.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F360/1/2/3/4/5/6/7 implement 32 kB of
this program memory space as in-system, re-programmable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x7BFF. Addresses above 0x7BFF are reserved on the 32 kB devices.
The C8051F368/9 implement 16 kB of Flash from addresses 0x0000 to 0x3FFF.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “13. Flash Memory” on page 135 for further details.



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