SN8F27E64LKB datasheet(74/192 Pages) SONIX

74 / 192 page

SN8F27E60 Series

8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD

Page 74

Version 1.4

6.11 T1 INTERRUPT OPERATION

When the T1C (T1CH, T1CL) counter occurs overflow, the T1

IRQ will be set to “1” however the T1IEN is enable or

disable. If the T1IEN = 1, the trigger event will make the T1

IRQ to be “1” and the system enter interrupt vector. If the

T1IEN = 0, the trigger event will make the T1

IRQ to be “1” but the system will not enter interrupt vector. Users need to

care for the operation under multi-interrupt situation.



Example: T1 interrupt request setup.

B0BCLR

FT1IEN

; Disable T1 interrupt service

B0BCLR

FT1ENB

; Disable T1 timer

MOV

A, #20H

;

B0MOV

T1M, A

; Set T1 clock = Fcpu / 32 and falling edge trigger.

CLR

T1CH

CLR

T1CL

B0BSET

FT1IEN

; Enable T1 interrupt service

B0BCLR

FT1IRQ

; Clear T1 interrupt request flag

B0BSET

FT1ENB

; Enable T1 timer

B0BSET

FGIE

; Enable GIE

Example: T1 interrupt service routine.

ORG

0FH

; Interrupt vector

JMP

INT_SERVICE

INT_SERVICE:

B0BTS1

FT1IRQ

; Check T1IRQ

JMP

EXIT_INT

; T1IRQ = 0, exit interrupt vector

B0BCLR

FT1IRQ

; Reset T1IRQ

B0MOV

A, T1CH

B0MOV

T1CHBUF, A

B0MOV

A, T1CL

B0MOV

T1CLBUF, A

; Save pulse width.

CLR

T1CH

CLR

T1CL

…

; T1 interrupt service routine

…

EXIT_INT:

RETI

; Exit interrupt vector

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