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SN8F27E64LKB Datasheet(PDF) 94 Page - SONiX Technology Company

Part # SN8F27E64LKB
Description  8-Bit Flash Micro-Controller with Embedded ICE and ISP
PDF  192 Pages
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Manufacturer  SONIX [SONiX Technology Company]
Direct Link  http://www.sonix.com.tw
Logo SONIX - SONiX Technology Company

SN8F27E64LKB Datasheet(HTML) 94 Page - SONiX Technology Company

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SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SONiX TECHNOLOGY CO., LTD
Page 94
Version 1.4
8.3.3 TC0M MODE REGISTER
TC0M is TC0 timer mode control register to configure TC0 operating mode including TC0 pre-scalar, clock source,
PWM function…These configurations must be setup completely before enabling TC0 timer.
0B4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC0M
TC0ENB
TC0rate2
TC0rate1
TC0rate0
TC0CKS1
TC0CKS0
-
PWM0OUT
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
After reset
0
0
0
0
0
0
-
0
Bit 0
PWM0OUT: PWM output control bit.
0 = Disable PWM output function, and P5.1 is GPIO mode.
1 = Enable PWM output function, and P5.1 outputs PWM signal.
Bit 2
TC0CKS0: TC0 clock source select bit.
0 = Fcpu.
1 = Fhosc.
Bit 3
TC0CKS1: TC0 clock source select bit.
0 = Internal clock (Fcpu and Fhosc controlled by TC0CKS0 bit).
1 = External input pin (P0.0/INT0) and enable event counter function. TC0rate[2:0] bits are useless.
Bit [6:4]
TC0RATE[2:0]: TC0 timer clock source select bits.
TC0CKS0=0 -> 000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4,
110 = Fcpu/2,111 = Fcpu/1.
TC0CKS0=1 -> 000 = Fhosc/128, 001 = Fhosc/64, 010 = Fhosc/32, 011 = Fhosc/16, 100 = Fhosc/8,
101 = Fhosc/4, 110 = Fhosc/2,111 = Fhosc/1.
Bit 7
TC0ENB: TC0 counter control bit.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
8.3.4 TC0C COUNTING REGISTER
TC0C is TC0 8-bit counter. When TC0C overflow occurs, the TC0IRQ flag is set as
“1” and cleared by program. The
TC0C decides TC0 interval time through below equation to calculate a correct value. It is necessary to write the correct
value to TC0C register and TC0R register first time, and then enable TC0 timer to make sure the fist cycle correct.
After one TC0 overflow occurs, the TC0C register is loaded a correct value from TC0R register automatically, not
program.
0B5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC0C
TC0C7
TC0C6
TC0C5
TC0C4
TC0C3
TC0C2
TC0C1
TC0C0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * TC0 clock rate)



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