SN8F27E64LKB datasheet(18/192 Pages) SONIX

18 / 192 page

SN8F27E60 Series

8-Bit Flash Micro-Controller with Embedded ICE and ISP

SONiX TECHNOLOGY CO., LTD

Page 18

Version 1.4

2.1.2 INTERRUPT VECTOR (0008H~0014H)

A 13-word vector address area is used to execute interrupt request. If any interrupt service executes, the program

counter (PC) value is stored in stack buffer and jump to 0008h~0014h of program memory to execute the vectored

interrupt. This interrupt is multi-vector and each of interrupts points to unique vector. Users have to define the interrupt

vector. The following example shows the way to define the interrupt vector in the program memory.



Note:

The “PUSH” and “POP” operations aren’t through instruction (PUSH, POP) and can executed save

and load ACC and working registers (0x80~0x8F) by hardware automatically.

ROM

Priority

0008H

WAKE Interrupt vector

0009H

INT0 Interrupt vector

000AH

INT1 Interrupt vector

000BH

T0 Interrupt vector

000CH

TC0 Interrupt vector

000DH

TC1 Interrupt vector

000EH

TC2 Interrupt vector

000FH

T1 Interrupt vector

0010H

ADC Interrupt vector

0011H

SIO Interrupt vector

0012H

MSP Interrupt vector

0013H

UART RX Interrupt vector

0014H

UART TX Interrupt vector

When one interrupt request occurs, and the program counter points to the correlative vector to execute interrupt

service routine. If WAKE interrupt occurs, the program counter points to ORG 8. If INT0 interrupt occurs, the program

counter points to ORG 9. In normal condition, several interrupt requests happen at the same time. So the priority of

interrupt sources is very important, or the system doesn’t know which interrupt is processed first. The interrupt priority

is follow vector sequence. ORG 8 is priority 1. ORG 9 is priority 2. In the case, the interrupt processing priority is as

following.

If WAKE, T0, TC2, T1 and SIO interrupt requests happen at the same time, the system processing interrupt sequence

is WAKE, T0, TC2, T1, and then SIO. The system processes WAKE interrupt service routine first, and then processes

T0 interrupt routine…Until finishing processing all interrupt requests.



Example:

Interrupt Request Occurrence Sequence: (2~8 interrupt requests occur during WAKE interrupt service routine

execution.)

WAKE

ADC

TC1

SIO

INT0

UART RX

Interrupt Processing Sequence:

WAKE

INT0

TC1

ADC

SIO

UART RX

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