PIC16F18323-ESLASHRF datasheet(103/442 Pages) MICROCHIP

103 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 103

PIC16(L)F18313/18323

8.3

CPUDOZE: DOZE AND IDLE REGISTER

VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0

R/W-0/0

R/W-1/1

—

—VREGPM<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-2

Unimplemented:

Read as ‘0’

bit 1-0

VREGPM<1:0>:

Voltage Regulator Power Mode Selection bits

= Lowest Power mode; LDO is off; Band gap generator is on only if needed by peripherals; longest wake-up time

= Low-Power mode; LDO is off; Band gap generator is on

= Normal-Power mode (Reset default); LDO supplying low power

= High-Power mode; LDO supplying highest power; fastest wake-up time

Note

PIC16F18313/18323 only.

R/W-0/u

R/W/HC/HS-0/0

R/W-0/0

U-0

R/W-0/0

IDLEN

DOZEN(1,2)

ROI

DOE

—

DOZE<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

IDLEN:

Idle Enable bit

=A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)

=A SLEEP instruction places the device into Full Sleep mode

bit 6

DOZEN:

Doze Enable bit(1,2)

= The CPU executes instruction cycles according to DOZE setting

= The CPU executes all instruction cycles (fastest, highest power operation)

bit 5

ROI:

Recover-on-Interrupt bit

= Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation.

= Interrupt entry does not change DOZEN

bit 4

DOE:

Doze on Exit bit

= Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.

= RETFIE does not change DOZEN

bit 3

Unimplemented:

Read as ‘0’

bit 2-0

DOZE<2:0>:

Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

111

= 1:256

110

=1:128

101

=1:64

100

=1:32

011

=1:16

010

=1:8

001

=1:4

000

=1:2

Note

When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.

Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.

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