LM5176PWPR datasheet(24/45 Pages) TI2

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IN(MIN)

OUT

RIPPLE(COUT)

OUT

u ¨

(21)

Typically, a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current

capacity. The complete schematic in Figure 8-1 shows a good starting point for COUT for typical applications.

8.2.2.6 Input Capacitor

In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given

by:

CIN(RMS)

OUT

D (1 D)

(22)

The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT / 2 = 3 A. A combination of ceramic

and bulk capacitors should be used to provide a short path for high di/dt current and to reduce the output voltage

ripple. The complete schematic in Figure 8-1 is a good starting point for CIN for typical applications.

8.2.2.7 Sense Resistor (RSENSE)

The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set

high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is

given by:

SENSE(BUCK)

OUT(MAX)

80 mV

13 m

(23)

For the boost mode of operation, the current limit resistor is given by:

SENSE(BOOST)

L(PEAK)

120 mV

8.3 m

(24)

The closest standard value of RSENSE = 8 mΩ is selected based on the boost mode operation.

The maximum power dissipation in RSENSE happens at VIN(MIN):

˜ ¨

IN(MIN)

RSENSE(MAX)

SENSE

OUT

120mV

0.9 W

(25)

Therefore, a sense resistor with 2-W power rating will be sufficient for this application.

For some application circuits, it can be required to add a filter network to attenuate noise in the CS and CSG

sense lines. See Figure 8-1 for typical values. The filter resistance should not exceed 100 Ω.

8.2.2.8 Slope Compensation

For stable current loop operation and to avoid subharmonic oscillations, the slope capacitor should be selected

based on Equation 26:

SLOPE

SENSE

4.7 H

2 S

235 pF

8 m

P u

: u

(26)

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one

switching cycle. Theoretically, a current mode loop is stable with half the “dead-beat” slope (twice the calculated

slope capacitor value in Equation 26). A smaller slope capacitor results in larger slope signal which is better for

noise immunity in the transition region (VIN~VOUT). A larger slope signal, however, restricts the achievable input

LM5176

SNVSAI1D – JUNE 2017 – REVISED AUGUST 2021

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