LM5176PWPR datasheet(25/45 Pages) TI2

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voltage range for a given output voltage, switching frequency, and inductor. For this design, CSLOPE = 220 pF is

selected for better transition region behavior while still providing the required VIN range. This selection of slope

capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Section

7.3.13.

8.2.2.9 UVLO

The UVLO resistor divider must be designed for turnon below 6 V. Selecting RUV2 = 249 kΩ gives a UVLO

hysteresis of 0.8 V based on Equation 2. The lower UVLO resistor is the selected using Equation 27:

UV2

EN(OP)

UV1

EN(STBY)

UV2

EN(OP)

(27)

A standard value of 59.0 kΩ is selected for RUV1.

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs

with gate (Miller) plateau voltage lower than the minimum VIN.

8.2.2.10 Soft-Start Capacitor

The soft-start time is programmed using the soft-start capacitor. The relationship between CSS and the soft-start

time is given by:

REF

(28)

CSS = 0.1 µF gives a soft-start time of 16 ms.

8.2.2.11 Dither Capacitor

The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching

frequency. A larger CDITH results in lower modulation frequency. For proper operation, the modulation frequency

(FMOD) must be much lower than the switching frequency. Use Equation 29 to select CDITH for the target

modulation frequency.

DITH

MOD

0.24 V

(29)

For the current design, dithering is not being implemented. Therefore, a 0-Ω resistor from the DITH pin to AGND

disables this feature.

8.2.2.12 MOSFETs QH1 and QL1

The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 50 V. In addition, they

must withstand the transient spikes at SW1 during switching. Therefore, QH1 and QL1 should be rated for 60 V

or higher. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the

converter, otherwise the MOSFETs may not fully enhance during start-up or overload conditions.

The power loss in QH1 in the boost mode of operation is approximated by:

OUT

COND(QH1)

OUT

DSON(QH1)

(30)

The power loss in QH1 in buck mode of operation consists of both conduction and switching loss components

given by Equation 31 and Equation 32, respectively:

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LM5176

SNVSAI1D – JUNE 2017 – REVISED AUGUST 2021

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