STM32WBA62CGF6 datasheet(157/185 Pages) STMICROELECTRONICS

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DS14736 Rev 1

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STM32WBA6xxx

Electrical characteristics

169

5.3.27

Timer characteristics

The parameters given in Table 90, Table 91, and Table 92 are specified by design. Refer to

Section 4.2 for details on the input/output alternate function characteristics (output compare,

input capture, external clock, PWM output).

3. Refer to Table 43: Embedded internal voltage reference.

4. No VREFINT division, includes only buffer consumption.

5. VREFINT division, includes resistor bridge and buffer consumption.

6. Evaluated by characterization, not tested in production.

7. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 75: I/O static characteristics.

Table 90. TIMx(1) characteristics(2)

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

-1

tTIMxCLK

fTIMxCLK = 100 MHz

fEXT

Timer external clock frequency

on CH1 to CH4

-0

fTIMxCLK/2

MHz

fTIMxCLK = 100 MHz

ResTIM

Timer resolution

TIM1, TIM3, TIM16, TIM17

bit

TIM2, TIM4

tCOUNTER16 16-bit counter period

-1

216

tTIMxCLK

fTIMxCLK = 100 MHz

0.01

655.36

µs

tCOUNTER32 32-bit counter period

-1

232

tTIMxCLK

fTIM2CLK = 100 MHz

0,01

42.94

1. TIMx, is used as a general term, where x stands for 1, 2, 3, 4, 16, or 17.

2. Specified by design, not tested in production.

Table 91. IWDG min/max timeout period at 32 kHz(1)(2)

Prescaler divider

PR[3:0] bits

Min timeout RL[11:0] = 0x002

Max timeout RL[11:0] = 0xFFF

Unit

0.325

512

0.750

1024

/16

1.500

2048

/32

3.0

4096

/64

6.0

8192

/128

12.0

16384

/256

24.0

32768

/512

48.0

65536

/1024

Others

96.0

131072

1. The exact timings depend upon the phasing of the APB interface clock vs. the IWDG kernel clock, hence there is always a

full kernel clock period of uncertainty.

2. Specified by design, not tested in production.

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