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STM32WBA62CGF6 Datasheet(PDF) 163 Page - STMicroelectronics |
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STM32WBA62CGF6 Datasheet(HTML) 163 Page - STMicroelectronics |
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163 / 185 page ![]() DS14736 Rev 1 163/185 STM32WBA6xxx Electrical characteristics 169 Figure 36. SPI timing diagram - Slave mode and CPHA = 1 Figure 37. SPI timing diagram - Master mode 5.3.31 SAI characteristics Unless otherwise specified, the parameters given in Table 96 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 30, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • I/O compensation cell activated • Measurement points are done at CMOS levels: 0.5 VDD MSv41659V2 th(SI) tc(SCK) tw(SCKH) tw(SCKL) tsu(NSS) ta(SO) tv(SO) th(NSS) tdis(SO) tsu(SI) NSS input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output MOSI input First bit OUT Next bits OUT Last bit OUT First bit IN Last bit IN Next bits IN th(SO) ai14136e th(MI) tc(SCK) tw(SCKH) tw(SCKL) tsu(MI) NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MOSI output MISO input First bit OUT Last bit OUT Next bits OUT First bit IN Last bit IN Next bits IN CPHA=1 CPOL=0 CPHA=1 CPOL=1 High tv(MO) th(MO) |
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