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ECP2 Datasheet(PDF) 37 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 37 Page - Lattice Semiconductor |
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37 / 386 page  2-34 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges Clock Transfer Registers ONEG1 CLKA TO OPOS1 TD DQ DQ DQ 0 1 0 1 0 1 DQ DQ DQ 0 1 0 1 D Q D-Type * D Q Latch D Q 0 1 0 1 0 1 0 1 ONEG0 OPOS0 DO Programmable Control Programmable Control 0 1 ECLK1 ECLK2 CLK1 Tristate Logic Tristate Logic Output Logic True PIO (A) in LVDS I/O Pair ONEG1 CLKB TO OPOS1 TD D Q D Q D Q 0 1 0 1 0 1 D Q D-Type /LATCH D-Type /LATCH D-Type /LATCH D-Type /LATCH DQ DQ 0 1 0 1 D Q DQ Latch D-Type D-Type Latch Latch D-Type Latch D-Type Latch DQ ONEG0 OPOS0 DO ECLK1 ECLK2 CLK1 Output Logic Comp PIO (B) in LVDS I/O Pair (CLKB) (CLKA) D-Type * D-Type* D-Type* Clock Transfer Registers DDR Output Registers DDR Output Registers * Shared with input register Note: Simplified version does not show CE and SET/RESET details 0 1 DQSXFER DQSXFER 0 1 0 1 |
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