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ECP2 Datasheet(PDF) 76 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 76 Page - Lattice Semiconductor |
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76 / 386 page  3-24 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet tDQVBS Data Valid Before DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI tDQVAS Data Valid After DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI fMAX_DDR2 DDR Clock Frequency ECP2/M 133 266 133 200 133 166 MHz SPI4.2 I/O Pin Parameters Static Alignment 4, 8, 11 Maximum Data Rate ECP2-20 — 750 — 622 — 622 Mbps ECP2-35 — 750 — 622 — 622 Mbps ECP2-50 — 750 — 622 — 622 Mbps ECP2-70 — 750 — 622 — 622 Mbps ECP2M20 — 622 — 622 — 622 Mbps ECP2M35 — 622 — 622 — 622 Mbps ECP2M50 — 622 — 622 — 622 Mbps ECP2M70 — 622 — 622 — 622 Mbps ECP2M100 — 622 — 622 — 622 Mbps tDVACLKSPI Data Valid After CLK (Receive) ECP2-20 — 0.25 — 0.25 — 0.25 UI ECP2-35 — 0.25 — 0.25 — 0.25 UI ECP2-50 — 0.25 — 0.25 — 0.25 UI ECP2-70 — 0.25 — 0.25 — 0.25 UI ECP2M20 — 0.21 — 0.21 — 0.21 UI ECP2M35 — 0.21 — 0.21 — 0.21 UI ECP2M50 — 0.21 — 0.21 — 0.21 UI ECP2M70 — 0.21 — 0.21 — 0.21 UI ECP2M100 — 0.21 — 0.21 — 0.21 UI tDVECLKSPI Data Hold After CLK (Receive) ECP2-20 0.75 — 0.75 — 0.75 — UI ECP2-35 0.75 — 0.75 — 0.75 — UI ECP2-50 0.75 — 0.75 — 0.75 — UI ECP2-70 0.75 — 0.75 — 0.75 — UI ECP2M20 0.79 — 0.79 — 0.79 — UI ECP2M35 0.79 — 0.79 — 0.79 — UI ECP2M50 0.79 — 0.79 — 0.79 — UI ECP2M70 0.79 — 0.79 — 0.79 — UI ECP2M100 0.79 — 0.79 — 0.79 — UI tDIASPI Data Invalid After Clock (Transmit) ECP2-20 — 280 — 280 — 280 ps ECP2-35 — 280 — 280 — 280 ps ECP2-50 — 280 — 280 — 280 ps ECP2-70 — 280 — 280 — 280 ps ECP2M20 — 230 — 230 — 230 ps ECP2M35 — 230 — 230 — 230 ps ECP2M50 — 230 — 230 — 230 ps ECP2M70 — 230 — 230 — 230 ps ECP2M100 — 230 — 230 — 230 ps LatticeECP2/M External Switching Characteristics 9 (Continued) Over Recommended Operating Conditions Parameter Description Device -7 -6 -5 Units Min. Max. Min. Max. Min. Max. |
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