ECP2 datasheet(40/386 Pages) LATTICE

40 / 386 page

2-37

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-34. DQS Input Routing for the Bottom Edge of the Device

DLL Calibrated DQS Delay Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock

(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS delay element to

a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of

the clock to the sync registers in the input register blocks. Figure 2-35 and Figure 2-36 show how the DQS transi-

tion signals are routed to the PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

(6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates

DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt-

age and process variations by the system clock and feedback loop.

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS

Delay

sysIO

Buffer

PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO B

PIO A

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

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