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ECP2 Datasheet(PDF) 87 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 87 Page - Lattice Semiconductor |
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87 / 386 page  3-35 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet sysCLOCK GPLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ. Max. Units fIN Input Clock Frequency (CLKI, CLKFB) Without external capacitor 20 — 420 MHz With external capacitor 5, 6 2 — 420 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) Without external capacitor 20 — 420 MHz With external capacitor 5 5 — 50 MHz fOUT2 K-Divider Output Frequency (CLKOK) Without external capacitor 0.156 — 210 MHz With external capacitor 5 0.039 — 25 MHz fVCO PLL VCO Frequency 640 — 1280 MHz fPFD Phase Detector Input Frequency Without external capacitor 20 — 420 MHz With external capacitor 5, 6 2 — 50 MHz AC Characteristics tDT Output Clock Duty Cycle Default duty cycle selected 3 45 50 55 % tPH 4 Output Phase Accuracy — — ±0.05 UI tOPJIT 1 Output Clock Period Jitter fOUT ≥ 100 MHz — — ±125 ps 50 ≤ fOUT < 100 MHz — 0.025 UIPP fOUT < 50 MHz — — 0.04 UIPP tSK Input Clock to Output Clock Skew N/M = integer — — ±250 ps tW Output Clock Pulse Width At 90% or 10% 1 — — ns tLOCK 2 PLL Lock-in Time Without external capacitor — — 150 µs With external capacitor 5 — — 500 µs tPA Programmable Delay Unit 85 130 360 ps tIPJIT Input Clock Period Jitter — — ±200 ps tFBKDLY External Feedback Delay — — 10 ns tHI Input Clock High Time 90% to 90% 0.5 — — ns tLO Input Clock Low Time 10% to 10% 0.5 — — ns tRST RST Pulse Width (RESETM/RESETK) 15 — — ns Reset Signal Pulse Width (CNTRST) Without external capacitor 500 — — ns With external capacitor 5 20 — — µs 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. 5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin. 6. fOUT (max) = fIN * 10 for fIN < 5MHz. Timing v.A 0.11 |
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