ECP2 datasheet(100/386 Pages) LATTICE

100 / 386 page

3-48

DC and Switching Characteristics

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Figure 3-21. JTAG Port Timing Waveforms

Symbol

Parameter

Min

Max

Units

fMAX

TCK clock frequency

—

MHz

tBTCP

TCK [BSCAN] clock pulse width

—

tBTCPH

TCK [BSCAN] clock pulse width high

—

tBTCPL

TCK [BSCAN] clock pulse width low

—

tBTS

TCK [BSCAN] setup time

—

tBTH

TCK [BSCAN] hold time

—

tBTRF

TCK [BSCAN] rise/fall time

—

mV/ns

tBTCO

TAP controller falling edge of clock to valid output

—

tBTCODIS

TAP controller falling edge of clock to valid disable

—

tBTCOEN

TAP controller falling edge of clock to valid enable

—

tBTCRS

BSCAN test capture register setup time

—

tBTCRH

BSCAN test capture register hold time

—

tBUTCO

BSCAN test update register, falling edge of clock to valid output

—

tBTUODIS

BSCAN test update register, falling edge of clock to valid disable

—

tBTUPOEN

BSCAN test update register, falling edge of clock to valid enable

—

Timing v.A 0.11

TMS

TDI

TCK

TDO

Data to be

captured

from I/O

Data to be

driven out

to I/O

Data Captured

tBTCPH

tBTCPL

tBTCOEN

tBTCRS

tBTUPOEN

tBUTCO

tBTUODIS

tBTCRH

tBTCO

tBTCODIS

tBTS

tBTH

tBTCP

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