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DS1006 Pinout Information_01.9

August 2008

Data Sheet DS1006

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

Signal Descriptions

Signal Name

I/O

Description

General Purpose

P[Edge] [Row/Column Number*]_[A/B]

I/O

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-

ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

[A/B] indicates the PIO within the PIC to which the pad is connected. Some of

these user-programmable pins are shared with special function pins. These

pins, when not used as special purpose pins, can be programmed as I/Os for

user logic. During conﬁguration the user-programmable I/Os are tri-stated

with an internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor enabled

after conﬁguration.

GSRN

Global RESET signal (active low). Any I/O pin can be GSRN.

—

No connect.

GND

—

Ground. Dedicated pins.

VCC

—

Power supply pins for core logic. Dedicated pins.

VCCAUX

—

Auxiliary power supply pin. This dedicated pin powers all the differential and

referenced input buffers.

VCCIOx

—

Dedicated power supply pins for I/O bank x.

VCCPLL

—

PLL supply pins. Should be tied to VCC even when the corresponding PLL is

unused.

VREF1_x, VREF2_x

—

Reference supply pins for I/O bank x. Pre-determined pins in each bank are

assigned as VREF inputs. When not used, they may be used as I/O pins.

XRES

—

10K ohm +/-1% resistor must be connected between this pad and ground.

PLLCAP

—

External capacitor connection for PLL.

PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

[LOC][num]_VCCPLL

—

Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center.

[LOC][num]_GPLL[T, C]_IN_A

General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row

from center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_GPLL[T, C]_FB_A

Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_SPLL[T, C]_IN_A

Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_SPLL[T, C]_FB_A

Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row

from center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_DLL[T, C]_IN_A

DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and

C = complement, index A,B,C...at each side.

[LOC][num]_DLL[T, C]_FB_A

Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

PCLK[T, C]_[n:0]_[3:0]

Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0,1,2,3 within bank.

LatticeECP2/M Family Data Sheet

Pinout Information

ECP2 Datasheet(PDF) 102 Page - Lattice Semiconductor

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