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ECP2 Datasheet(PDF) 80 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 80 Page - Lattice Semiconductor |
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80 / 386 page  3-28 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet LatticeECP2/M Internal Switching Characteristics 1 Over Recommended Operating Conditions Parameter Description -7 -6 -5 Units Min. Max. Min. Max. Min. Max. PFU/PFF Logic Mode Timing tLUT4_PFU LUT4 delay (A to D inputs to F output) — 0.180 — 0.198 — 0.216 ns tLUT6_PFU LUT6 delay (A to D inputs to OFX output) — 0.304 — 0.331 — 0.358 ns tLSR_PFU Set/Reset to output of PFU (Asynchro- nous) — 0.600 — 0.655 — 0.711 ns tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.128 — 0.129 — 0.129 — ns tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.051 — -0.049 — -0.046 — ns tSUD_PFU Clock to D input setup time 0.061 — 0.071 — 0.081 — ns tHD_PFU Clock to D input hold time 0.002 — 0.003 — 0.003 — ns tCK2Q_PFU Clock to Q delay, (D-type Register Configu- ration) — 0.285 — 0.309 — 0.333 ns PFU Dual Port Memory Mode Timing tCORAM_PFU Clock to Output (F Port) — 0.902 — 1.083 — 1.263 ns tSUDATA_PFU Data Setup Time -0.172 — -0.205 — -0.238 — ns tHDATA_PFU Data Hold Time 0.199 — 0.235 — 0.271 — ns tSUADDR_PFU Address Setup Time -0.245 — -0.284 — -0.323 — ns tHADDR_PFU Address Hold Time 0.246 — 0.285 — 0.324 — ns tSUWREN_PFU Write/Read Enable Setup Time -0.122 — -0.145 — -0.168 — ns tHWREN_PFU Write/Read Enable Hold Time 0.132 — 0.156 — 0.180 — ns PIC Timing PIO Input/Output Buffer Timing tIN_PIO Input Buffer Delay (LVCMOS25) — 0.613 — 0.681 — 0.749 ns tOUT_PIO Output Buffer Delay (LVCMOS25) — 1.115 — 1.115 — 1.343 ns IOLOGIC Input/Output Timing tSUI_PIO Input Register Setup Time (Data Before Clock) 0.596 — 0.645 — 0.694 — ns tHI_PIO Input Register Hold Time (Data after Clock) -0.570 — -0.614 — -0.658 — ns tCOO_PIO Output Register Clock to Output Delay — 0.61 — 0.66 — 0.72 ns tSUCE_PIO Input Register Clock Enable Setup Time 0.032 — 0.037 — 0.041 — ns tHCE_PIO Input Register Clock Enable Hold Time -0.022 — -0.025 — -0.028 — ns tSULSR_PIO Set/Reset Setup Time 0.184 — 0.201 — 0.217 — ns tHLSR_PIO Set/Reset Hold Time -0.080 — -0.086 — -0.093 — ns EBR Timing tCO_EBR Clock (Read) to output from Address or Data — 2.51 — 2.75 — 2.99 ns tCOO_EBR Clock (Write) to output from EBR output Register — 0.33 — 0.36 — 0.39 ns tSUDATA_EBR Setup Data to EBR Memory -0.157 — -0.181 — -0.205 — ns tHDATA_EBR Hold Data to EBR Memory 0.173 — 0.195 — 0.217 — ns tSUADDR_EBR Setup Address to EBR Memory -0.115 — -0.130 — -0.145 — ns tHADDR_EBR Hold Address to EBR Memory 0.138 — 0.155 — 0.172 — ns tSUWREN_EBR Setup Write/Read Enable to PFU Memory -0.128 — -0.149 — -0.170 — ns |
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