ECP2 datasheet(19/386 Pages) LATTICE

19 / 386 page

2-16

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices

have four secondary clocks (SC0 to SC3) which are distrubed to every region.

The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the

secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for

high fan-out signals.

Figure 2-15. Secondary Clock Regions ECP2-50

I/O Bank 0

I/O Bank 1

I/O Bank 5

I/O Bank 4

Secondary Clock

Region 1

Secondary Clock

Region 2

Secondary Clock

Region 3

Secondary Clock

Region 4

Secondary Clock

Region 5

Secondary Clock

Region 6

Secondary Clock

Region 7

Secondary Clock

Region 8

Vertical Routing

Channel Regional

Boundary

EBR Row

Regional

Boundary

DSP Row

Regional

Boundary

DSP Row

Regional

Boundary

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