38D2 datasheet(37/136 Pages) RENESAS

37 / 136 page

Rev.3.02

Apr 10, 2008

Page 37 of 131

REJ03B0177-0302

38D2 Group

(4) Set of Timer X Mode Register

Set the write control bit of the timer X mode register to “1”

(write to the latch only) when setting the IGBT output and PWM

modes.

Output waveform simultaneously reflects the contents of both

registers at the next underflow after writing to the timer X

(5) Output Control Function of Timer X

• When using the output control function (INT1 and INT2) in the

IGBT output mode, set the levels of INT1 and INT2 to “H” in

the falling edge active or to “L” in the rising edge active before

switching to the IGBT output mode.

(6) Switch of CNTR0 Active Edge

• When the CNTR0 active edge switch bits are set, at the same

time, the interrupt active edge is also affected.

When the pulse width is measured, set the bit 7 of the CNTR0

active edge switch bits to “0”.

(7) When Timer X Pulse Width Measurement Mode

Used

When timer X pulse width measurement mode is used, enable the

event counter wind control data (bit 5 of timer X mode register

(address 002D16)) by setting to “0”.

If the event counter window control data (bit 5 of timer X mode

enable/disable the CNTR0 input, the input is not accepted after

the timer 1 underflow.

Fig. 28 Structure of timer X related registers

Timer X mode register

(TXM: address 002D16)

Timer X operating mode bits

b2b1b0

0 0 0 : Timer mode

0 0 1 : Pulse output mode

0 1 0 : IGBT output mode

0 1 1 : PWM mode

1 0 0 : Event counter mode

1 0 1 : Pulse width measurement mode

1 1 0 : Not available

1 1 1 : Not available

Timer X write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer X count source selection bit

0 : Frequency divider output

1 : f(XCIN)

Data for control of event counter window

0 : Event count enabled

1 : Event count disabled

Timer X count stop bit

0 : Count operation

1 : Count stop

Timer X output 1 selection bit (P35)

0 : I/O port

1 : Timer X output 1

Timer X control register 1

(TXCON1: address 002E16)

Noise filter sampling clock selection bit

0 : f(XIN)/2

1 : f(XIN)/4

External trigger delay time selection bits

b2b1

0 0 : Not delayed

0 1 : (4/f(XIN))

μs

1 0 : (8/f(XIN))

μs

1 1 : (16/f(XIN))

μs

Timer X output control bit 1 (P51)

0 : Not used INT1 interrupt signal

1 : INT1 interrupt signal used

Timer X output control bit 2 (P34)

0 : Not used INT2 interrupt signal

1 : INT2 interrupt signal used

Timer X output 1 active edge switch bit

0 : Start at “L” output

1 : Start at “H” output

CNTR0 active edge switch bits

b7b6

0 0 : Count at rising edge in event counter mode

Falling edge active for CNTR0 interrupt

Measure “H” pulse width in pulse width measurement mode

0 1 : Count at falling edge in event counter mode

Rising edge active for CNTR0 interrupt

Measure “L” pulse width in pulse width measurement mode

1 0 :

Count at both edges in event counter mode

1 1 :

Both edges active for CNTR0 interrupt

Timer X control register 2

(TXCON2: address 002F16)

Timer X output 2 control bit (P37)

0 : I/O port

1 : Timer X output 2

Timer X output 2 active edge switch bit

0 : Start at “L” output

1 : Start at “H” output

Timer X dividing frequency selection bits

b3b2

0 0 : 1/16

× φ SOURCE

0 1 : 1/1

× φ SOURCE

1 0 : 1/2

× φ SOURCE

1 1 : 1/256

× φ SOURCE

Trigger for IGBT input control bit

0 : Noise filter sampling clock

× 1

External trigger delay time

× 1

1 : Noise filter sampling clock

× 2

External trigger delay time

× 1/2

Not used (returns “0” when read)

(1)

Note1:

φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

38D2 Datasheet(PDF) 37 Page - Renesas Technology Corp

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