38D2 datasheet(97/136 Pages) RENESAS

97 / 136 page

Rev.3.02

Apr 10, 2008

Page 97 of 131

REJ03B0177-0302

38D2 Group

NOTES:

1. Relationship between system clock

φ frequency and power source voltage is shown in the graph below.

2. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.

3. 12.5 MHz

< f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

4. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and

operation temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency

oscillator.

5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

<System clock

φ frequency>

Table 24 Recommended operating conditions (4)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta =

−20 to 85°C, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Unit

Min.

Typ.

Max.

f(CNTR0)

f(CNTR1)

Timer X and Timer Y

Input frequency (duty cycle 50%)

4.5

≤ VCC ≤ 5.5V

6.25

MHz

4.0

≤ VCC < 4.5V

× Vcc −4MHz

2.0

≤ VCC < 4.0V

Vcc

MHz

VCC

< 2.0V

× Vcc −8MHz

f(Tclk)

Timer X, Timer Y,

Timer 1, Timer 2,

Timer 3, Timer 4 clock input frequency

(Count source frequency of each timer)

4.5

≤ VCC ≤ 5.5V

MHz

4.0

≤ VCC < 4.5V

× Vcc −8MHz

2.0

≤ VCC < 4.0V

× Vcc

MHz

VCC

< 2.0V

× Vcc −16

MHz

φ)

System clock

φ frequency (1)

4.5

≤ VCC ≤ 5.5V

6.25

MHz

4.0

≤ VCC < 4.5V

MHz

2.0

≤ VCC < 4.0V

Vcc

MHz

VCC

< 2.0V

× Vcc −8MHz

f(XIN)

Main clock input frequency

(duty cycle 50%) (2)(3)

4.5

≤ VCC ≤ 5.5V

1.0

MHz

2.0

≤ VCC < 4.5V

1.0

8.0

MHz

VCC

< 2.0V

1.0

× Vcc −32

MHz

f(XCIN)

Sub-clock oscillation frequency

(duty cycle 50%)(4)(5)

32.768

kHz

[MHz]

6.25

4.0

2.0

1.0

1.8 2.0

4.0 4.5

5.5 [V]

Power source voltage

[MHz]

8.0

4.0

1.0

1.8 2.0

4.5

5.5 [V]

Power source voltage

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