SH7616 datasheet(5/935 Pages) RENESAS

5 / 935 page

Rev. 2.00 Mar 09, 2006 page v of xxvi

Main Revisions in This Edition

Item

Page Revision (See Manual for Details)

All



• Company name amended

Hitachi, Ltd.

→ Renesas Technology Corp.

• Amendments made due to change in package code

FP-208C

→ PRQP0208KA-A

2.1.4 DSP Registers 37

Description added

Figure 2.4 shows the DSP registers. The DSR register bit functions

are shown in table 2.2. Registers A0, X0, X1, Y0, Y1, and DSR are

handled as system registers by CPU core instructions.

7.1.5 Address Map

Table 7.3 Address

Map

255

Table amended

Address

Space

Memory

Size

H'1000E000–H'1000EFFF

On-chip X RAM area

4 kbytes

H'1001E000–H'1001EFFF

On-chip Y RAM area

4 kbytes

7.2.7 Individual

Memory Control

Bits 1 and 15

• For synchronous

DRAM interface

Bits 7, 5, and 4

269 to

274

Description replaced

7.5.11 64 Mbit

Synchronous DRAM

(2 Mword

× 32-bit)

Connection

323

Description amended

Synchronous DRAM Mode Settings: To make mode settings for

the synchronous DRAM, write to address X+H'FFFF0000 or

X+H'FFFF8000 from the CPU. (X represents the setting value.)

Whether to use X+H'FFFF0000 or X+H'FFFF8000 determines on

the synchronous DRAM used.

8.4.7 Associative

Purges

Figure 8.11

Associative Purge

Access

369

Figure amended

Tag address

010

Entry

address

—

10 9

4 3

29 28

Associative purge:

Address

Bit

Number of bits

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