SH7616 datasheet(98/935 Pages) RENESAS

98 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 72 of 906

REJ09B0292-0200

Category

Mnemonic

14 13 12

7 6 5 4 3 2 1 0

if cc

0 *

Reserved

Reserved*2

Reserved

(if cc) PSHL Sx, Sy, Dz

(if cc) PSHA Sx, Sy, Dz

(if cc) PSUB Sx, Sy, Dz

(if cc) PADD Sx, Sy, Dz

(if cc) PAND Sx, Sy, Dz

(if cc) PXOR Sx, Sy, Dz

(if cc) POR Sx, Sy, Dz

(if cc) PDEC Sx, Dz

(if cc) PDEC Sy, Dz

(if cc) PINC Sx, Dz

(if cc) PINC Sy, Dz

(if cc) PCLR Dz

(if cc) PDMSB Sx, Dz

(if cc) PDMSB Sy, Dz

(if cc) PNEG Sx, Dz

(if cc) PNEG Sy, Dz

(if cc) PCOPY Sx, Dz

(if cc) PCOPY Sy, Dz

(if cc) PSTS MACH, Dz

(if cc) PSTS MACL, Dz

(if cc) PLDS Dz, MACL

(if cc) PLDS Dz, MACH

Conditional

three

operand

instructions

if cc

10:DCT

11:DCF

01:

Uncon-

dition

31–27

25–16

A field

Notes: 1. System reserved code

2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction)

* : Don't care

2.5

Instruction Set

The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP

data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a

number of CPU instructions for supporting the DSP functions. The instruction set is explained

below in terms of each of the three groups.

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