SH7616 datasheet(29/935 Pages) RENESAS

29 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 3 of 906

REJ09B0292-0200

Item

Specifications

DSP

• DSP engine

 Multiplier

 Arithmetic logic unit (ALU)

 Shifter

 DSP registers

• Multiplier

 16 bits × 16 bits → 32 bits

 Single-cycle multiplier

• DSP registers

 Two 40-bit data registers

 Six 32-bit data registers

 Modulo register (MOD, 32 bits) added to control registers

 Repeat counter (RC) added to status register (SR)

 Repeat start register (RS, 32 bits) and repeat end register (RE, 32 bits)

added to control registers

• DSP data bus

 Extended Harvard architecture

 Simultaneous access to two data buses and one instruction bus

• Parallel processing

 Maximum of four parallel processes

 ALU operations, multiplication, and two loads or stores

• Address processors

 Two address processors

 Address operations to access two memories

• DSP data addressing modes

 Increment and index

 Each with or without modulo addressing

• Repeat control: Zero-overhead repeat (loop) control

• Instruction set

 16-bit length (in case of load or store only)

 32-bit length (including ALU operations and multiplication)

 Added SuperH microcontroller instructions for accessing DSP registers

• Fifth and last pipeline stage is DSP stage

SH7616 Datasheet(PDF) 29 Page - Renesas Technology Corp