SH7616 datasheet(18/935 Pages) RENESAS

18 / 935 page

Rev. 2.00 Mar 09, 2006 page xviii of xxvi

9.2.8

PHY Interface Status Register (PSR)................................................................... 389

9.2.9

Transmit Retry Over Counter Register (TROCR) ............................................... 390

9.2.10 Single Collision Detect Counter Register (SCDCR)............................................ 391

9.2.11 Delay Collision Detect Counter Register (CDCR) .............................................. 392

9.2.12 Lost Carrier Counter Register (LCCR) ................................................................ 393

9.2.13 Carrier Not Detect Counter Register (CNDCR) .................................................. 394

9.2.14 Illegal Frame Length Counter Register (IFLCR)................................................. 395

9.2.15 CRC Error Frame Counter Register (CEFCR)..................................................... 396

9.2.16 Frame Receive Error Counter Register (FRECR )............................................... 397

9.2.17 Too-Short Frame Receive Counter Register (TSFRCR)...................................... 398

9.2.18 Too-Long Frame Receive Counter Register (TLFRCR)...................................... 399

9.2.19 Residual-Bit Frame Counter Register (RFCR) .................................................... 400

9.2.20 Multicast Address Frame Counter Register (MAFCR)........................................ 401

9.3

Operation .......................................................................................................................... 402

9.3.1

Transmission........................................................................................................ 402

9.3.2

Reception ............................................................................................................. 404

9.3.3

MII Frame Timing ............................................................................................... 406

9.3.4

Accessing MII Registers ...................................................................................... 408

9.3.5

Magic Packet Detection ....................................................................................... 411

9.3.6

CPU Operating Mode and Ethernet Controller Operation ................................... 412

9.3.7

CAM Match Signal Input Function...................................................................... 413

9.4

Connection to PHY-LSI.................................................................................................... 415

Section 10 Ethernet Controller Direct Memory Access Controller

(E-DMAC) ....................................................................................................... 417

10.1 Overview........................................................................................................................... 417

10.1.1 Features................................................................................................................ 417

10.1.2 Configuration ....................................................................................................... 418

10.1.3 Descriptor Management System .......................................................................... 419

10.1.4 Register Configuration......................................................................................... 419

10.2 Register Descriptions ........................................................................................................ 421

10.2.1 E-DMAC Mode Register (EDMR) ...................................................................... 421

10.2.2 E-DMAC Transmit Request Register (EDTRR).................................................. 422

10.2.3 E-DMAC Receive Request Register (EDRRR) ................................................... 423

10.2.4 Transmit Descriptor List Address Register (TDLAR) ......................................... 424

10.2.5 Receive Descriptor List Address Register (RDLAR) .......................................... 425

10.2.6 EtherC/E-DMAC Status Register (EESR) ........................................................... 426

10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ...................... 432

10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................ 437

10.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................... 438

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