SH7616 datasheet(9/935 Pages) RENESAS

9 / 935 page

Rev. 2.00 Mar 09, 2006 page ix of xxvi

Item

Page Revision (See Manual for Details)

11.3.6 DMA Transfer

Request

Acknowledge Signal

Output Timing

Figure 11.13 Example

of DACKn Output

Timing

496

Figure replaced

Clock

DACKn

(Active high)

Address bus

CPU

DMAC

0.5 cycles

14.3.4 Operation in

Synchronous Mode

613

Description amended

In synchronous mode, the SCIF receives data in synchronization

with the rise of the serial clock.

15.4 SIOF Interrupt

Sources and DMAC

663

Description amended

Each SIOF channel has four interrupt sources: the receive-overrun-

error interrupt (RERI0) request, transmit-underrun-error interrupt

(TERI0) request, receive-data-full interrupt/receive-control-data-

interrupt/transmit-control-data-register-empty interrupt (TDEI0)

request. Table 15.3 shows the interrupt sources and their relative

priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE,

RCIE, TIE, and TCIE bits, respectively, in SICTR. The RERI0 and

TERI0 interrupts cannot be disabled.

Table amended

Interrupt

Source

Description

DMAC

Activation

Priority

RERI0

Receive overrun error (RERR)

Not possible

TERI0

Transmit underrun error (TERR)

Not possible

RDFI0

Receive data register full (RDRF)/

Receive Control Data Register Full (RCD)

Possible*

TDEI0

Transmit data register empty (TDRE)/

Transmit Control Data Register Empty (TCD)

Possible*

High

↑

↓

Low

Table 15.3 SIOF

Interrupt Sources

664

Table amended

Abbreviation

Voltage

Operating

Frequency Mark Code

Package

SH7616

3.3 V

62.5 MHz

HD6417616SF

PLQP0208KA-A

Appendix C

Table C.1 SH7616

Product Lineup

904

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