SH7616 datasheet(6/935 Pages) RENESAS

6 / 935 page

Rev. 2.00 Mar 09, 2006 page vi of xxvi

Item

Page Revision (See Manual for Details)

10.2.8

Transmit/Receive

Status Copy Enable

437

Description amended

Bit:

. . .

——

—

———

Initial value:

. . .

000

R/W:

RRR

Bit:

——

———

Initial value:

R/W:

RRR

Bit:

543

210

RMAFCE

—

———

Initial value:

R/W:

R/W

RRR

Bits 31 to 8—Reserved These bits are always read as 0. The write value should always be 0.

Bit 7—Multicast Address Frame Receive (RMAF): Bit Copy Enable (RMAFCE)

Bit 7: RMAFCE

Description

Enables the RMAF bit status to be indicated in the RFS7 bit in the receive

descriptor.

Disables occurrence of corresponding source to be indicated in the RFS7 bit in

the receive descriptor.

Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.

10.3.1 Descriptor

List and Data Buffers

Transmit Descriptor 0

(TD0)

450

Description amended

TFS9

Bit 27—Transmit Frame Error (TFE): Indicates that one or other bit of the transmit frame status

indicated by bits 26 to 0 is set.

Bit 27: TFE

Description

No error during transmission

An error of some kind occurred during transmission (see bits 26 to 0)

Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0): These bits indicate the error status

during frame transmission.

• TFS26 to

—Reserved

• TFS8—Teransmit Abort Detect

Note: This bit is set to 1 wh

any of Transmit Frame Status bits 4 to 0 is set. When this bit is

set, the Transmit Frame Error bit (bit 27: TFE) is set to 1.

• TFS7 to TFS5—Reserved

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