SH7616 datasheet(31/935 Pages) RENESAS

Part #	SH7616

Description	32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PDF	935 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

31 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 5 of 906

REJ09B0292-0200

Item

Specifications

User break

controller (UBC),

4 channels

(A, B, C, D)

• Interrupt generation based on independent or sequential conditions for

channels A, B, C, D

 Three sequential setting patterns: A → B → C → D, B → C → D,

→ D

• Settable break conditions: Address, data (channels C and D only), bus

master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write,

operand cycle (byte/word/longword)

• User break interrupt generated on occurrence of break condition

• Processing can be stopped before or after instruction execution in

instruction fetch cycle

• Break with specification of number of executions (channels C and D only)

Settable number of executions: max. 2

12 – 1 (4095)

• PC trace function

Branch source/branch destination can be traced in branch instruction fetch

(max. 8 addresses (4 pairs))

SH7616 Datasheet(PDF) 31 Page - Renesas Technology Corp