R5F2L3ACBNFP datasheet(178/848 Pages) RENESAS

178 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 142 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

9. Clock Generation Circuit

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

Figure 9.5

Procedure for Switching Low-Speed On-Chip Oscillator to XIN Clock

Figure 9.6

Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog

Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt

OCD3 to OCD0: Bits in OCD register

Switch to XIN clock

Check several times

whether OCD3 bit is set to 0

(XIN clock oscillates)

Set bits OCD1 to OCD0 to 00b

Set OCD2 bit to 0

(XIN clock selected)

End

YES

Determination of

interrupt sources

OCD3 = 1?

(XIN clock stops)

OCD1 = 1

(oscillation stop detection

interrupt enabled) and OCD2 = 1

(on-chip oscillator clock

selected as the system clock)?

VW2C3 = 1?

(watchdog timer underflow)

VW2C2 = 1?

(Vdet2 passed)

To oscillation stop detection

interrupt routine

To voltage monitor 1

interrupt routine

To voltage monitor 2

interrupt routine

To watchdog timer

interrupt routine

YES

Note:

1. This disables multiple oscillation stop detection interrupts.

OCD1 to OCD3: Bits in OCD register

VW2C2, VW2C3: Bits in VW2C register

Set OCD1 bit to 0

(oscillation stop detection

interrupt disabled) (1)

R5F2L3ACBNFP Datasheet(PDF) 178 Page - Renesas Technology Corp

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