R5F2L3ACBNFP datasheet(206/848 Pages) RENESAS

206 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 170 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

12. Interrupts

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.1.2

Software Interrupts

A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.

12.1.2.1

Undefined Instruction Interrupt

An undefined instruction interrupt is generated when the UND instruction is executed.

12.1.2.2

Overflow Interrupt

An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO

instruction is executed. Instructions that set the O flag are as follows:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.

12.1.2.3

BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

12.1.2.4

INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to

63 can be specified with the INT instruction. Because software interrupt numbers are assigned to peripheral

function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing

the INT instruction.

For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and the U

flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack

when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change

state during instruction execution, and the selected SP is used.

R5F2L3ACBNFP Datasheet(PDF) 206 Page - Renesas Technology Corp