R5F2L3ACBNFP datasheet(207/848 Pages) RENESAS

207 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 171 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

12. Interrupts

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.1.3

Special Interrupts

Special interrupts are non-maskable.

12.1.3.1

Watchdog Timer Interrupt

A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 15. Watchdog Timer.

12.1.3.2

Oscillation Stop Detection Interrupt

An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the

oscillation stop detection function, refer to 9. Clock Generation Circuit.

12.1.3.3

Voltage Monitor 1/Comparator A1 Interrupt

A voltage monitor 1/Comparator A1 interrupt is generated by the voltage detection circuit or the comparator A.

A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the

voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32.

Comparator A.

12.1.3.4

Voltage Monitor 2/Comparator A2 Interrupt

A voltage monitor 2/Comparator A2 interrupt is generated by the voltage detection circuit or the comparator A.

A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the

voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32.

Comparator A.

12.1.3.5

Single-Step Interrupt, Address Break Interrupt

Do not use these interrupts. They are provided exclusively for use by development tools.

12.1.3.6

Address Match Interrupt

An address match interrupt is generated immediately before executing an instruction that is stored at an address

indicated by registers RMAD0 to RMAD1 if the AIER0 bit in the AIER0 register or AIER1 bit in the AIER1

For details of the address match interrupt, refer to 12.6 Address Match Interrupt.

12.1.4

Peripheral Function Interrupts

A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts

are maskable. Refer to Table 12.2 Relocatable Vector Tables for sources of the corresponding peripheral

function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral

functions.

R5F2L3ACBNFP Datasheet(PDF) 207 Page - Renesas Technology Corp

R5F2L3ACBNFP Datasheet(HTML) 207 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL