7540 datasheet(38/366 Pages) RENESAS

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1-19

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

HARDWARE

FUNCTIONAL DESCRIPTION

Fig. 17 Block diagram of ports (1)

(6)Port P11

Data bus

Port latch

Serial I/O1 output

P11/TxD1 P-channel output disable bit

(5)Port P10

(4)Ports P04–P07

(1)Port P00

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

CNTR1 interrupt input

(2)Ports P01, P02

Programmable waveform generation mode

Timer output

(7)Port P12

Serial I/O1, serial I/O2 clock output

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Serial I/O1 synchronous

clock selection bit

SCLK2 pin

selection bit

(3)Port P03

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

Timer output

P03/TXOUT

output valid

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

Direction

Data bus

Port latch

Serial I/O1 enable bit

Receive enable bit

Serial I/O1 input

P10, P12, P13

input level

selection bit

Direction

Serial I/O1 enable bit

Transmit enable bit

Direction

Data bus

Port latch

Serial I/O1, serial I/O2 clock input

P10, P12, P13

input level

selection bit

*P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.

P00 key-on wakeup

selection bit

When the TTL level is selected, there is no hysteresis characteristics.

P02/TZOUT;

Programmable waveform generation mode

Programmable one-shot generation mode

Programmable wait one-shot generation mode

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