7540 datasheet(68/366 Pages) RENESAS

68 / 366 page

1-49

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

HARDWARE

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after reset are

undefined except for the interrupt disable flag I which is “1”. After

reset, initialize flags which affect program execution. In particular,

it is essential to initialize the T flag and the D flag because of their

effect on calculations.

Interrupts

The contents of the interrupt request bit do not change even if the

BBC or BBS instruction is executed immediately after they are

changed by program because this instruction is executed for the

previous contents. For executing the instruction for the changed

contents, execute one instruction before executing the BBC or

BBS instruction.

Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag

D to “1”, then execute the ADC instruction or SBC instruction. In

this case, execute SEC instruction, CLC instruction or CLD in-

struction after executing one instruction before the ADC instruction

or SBC instruction.

• In the decimal mode, the values of the N (negative), V (overflow)

and Z (zero) flags are invalid.

Ports

• The values of the port direction registers cannot be read.

That is, it is impossible to use the LDA instruction, memory opera-

tion instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions such

as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read/modify/write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

A/D Conversion

Do not execute the STP instruction during A/D conversion.

Instruction Execution Timing

The instruction execution time can be obtained by multiplying the

frequency of the internal clock

φ by the number of cycles men-

tioned in the machine-language instruction table.

The frequency of the internal clock

φ is the same as that of the XIN

in double-speed mode, twice the XIN cycle in high-speed mode

and 8 times the XIN cycle in middle-speed mode.

CPU Mode Register

The oscillation mode selection bit and processor mode bits can be

rewritten only once after releasing reset. However, after rewriting it

is disable to write any value to the bit. (Emulator MCU is ex-

cluded.)

When a ceramic oscillation is selected, a double-speed mode of

the clock division ratio selection bits can be used. Do not use it

when an RC oscillation is selected.

State transition

Do not stop the clock selected as the operation clock because of

setting of CM3, 4.

NOTES ON HARDWARE

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the

capacitor to as close as possible. For bypass capacitor which

should not be located too far from the pins to be connected, a ce-

ramic capacitor of 0.01

µF to 0.1 µF is recommended.

One Time PROM Version

The CNVss pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVss

pin and Vss pin with 1 to 10 k

Ω resistance.

The mask ROM version track of CNVss pin has no operational in-

terference even if it is connected via a resistor.

NOTES ON PROGRAMMING/NOTES ON HARDWARE

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