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7540 Datasheet(PDF) 82 Page - Renesas Technology Corp |
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7540 Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 366 page  2-6 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port Fig. 2.1.8 Structure of Interrupt edge selection register Fig. 2.1.9 Structure of Interrupt request register 1 Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset RW 0 1 2 3 4 5 6 7 Name 0 0 0 0 0 0 0 0 Interrupt edge selection register (INTEDGE) [Address : 3A 16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. ✕ ✕ INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active P00 key-on wakeup enable bit ✕ ✕ ✕ 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset RW 0 1 2 3 4 5 6 7 Name 0 0 0 0 0 0 0 0 Interrupt request register 1 (IREQ1) [Address : 3C 16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR0 interrupt request bit CNTR1 interrupt request bit ✽: These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued ✽ ✽ ✽ ✽ ✽ ✽ ✽ Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued ✽ |
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