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7540 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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7540 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 366 page ![]() 1-20 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Fig. 18 Block diagram of ports (2) Pull-up control INT interrupt input P3 input level selection bit (11) Ports P30–P35 Pull-up control (9) Port P14 Data bus Serial I/O1 ready output Serial I/O2 output Serial I/O2 input SDATA2 pin selection bit Port latch Direction register SDATA2 output in operation signal CNTR0 interrupt input Pulse output mode Timer output P10, P12, P13 input level selection bit Serial I/O mode selection bit Serial I/O1 enable bit SRDY1 output enable bit P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register A/D converter input Analog input pin selection bit (12) Ports P36, P37 Data bus Port latch Direction register * * (10) Ports P20–P27 * (8) Port P13 When the TTL level is selected, there is no hysteresis characteristics. |
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