7540 datasheet(16/366 Pages) RENESAS

16 / 366 page

7540 Group

List of figures

Fig. 3.4.1 Selection of packages ............................................................................................... 3-92

Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-92

Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-93

Fig. 3.4.4 Wiring for CNVSS pin ................................................................................................ 3-93

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM ..................................................... 3-94

Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................ 3-94

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-95

Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-95

Fig. 3.4.9 Wiring of signal lines where potential levels change frequently ......................... 3-96

Fig. 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-96

Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-96

Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-97

Fig. 3.5.1 Structure of Port Pi (i = 0, 2, 3) .............................................................................. 3-98

Fig. 3.5.2 Structure of Port P1 ................................................................................................... 3-98

Fig. 3.5.3 Structure of Port Pi direction register (i = 0, 2, 3) ............................................... 3-99

Fig. 3.5.4 Structure of Port P1 direction register .................................................................... 3-99

Fig. 3.5.5 Structure of Pull-up control register ...................................................................... 3-100

Fig. 3.5.6 Structure of Port P1P3 control register ................................................................ 3-100

Fig. 3.5.7 Structure of Transmit/Receive buffer register ...................................................... 3-101

Fig. 3.5.8 Structure of Serial I/O1 status register ................................................................. 3-101

Fig. 3.5.9 Structure of Serial I/O1 control register ................................................................ 3-102

Fig. 3.5.10 Structure of UART control register ...................................................................... 3-102

Fig. 3.5.11 Structure of Baud rate generator ......................................................................... 3-103

Fig. 3.5.12 Structure of Timer A mode register .................................................................... 3-104

Fig. 3.5.13 Structure of Timer A register ............................................................................... 3-105

Fig. 3.5.14 Structure of Timer Y, Z mode register ............................................................... 3-105

Fig. 3.5.15 Structure of Prescaler Y, Prescaler Z ................................................................. 3-106

Fig. 3.5.16 Structure of Timer Y secondary, Timer Z secondary ....................................... 3-106

Fig. 3.5.17 Structure of Timer Y primary, Timer Z primary ................................................. 3-107

Fig. 3.5.18 Structure of Timer Y, Z waveform output control register ............................... 3-107

Fig. 3.5.19 Structure of Prescaler 1 ........................................................................................ 3-108

Fig. 3.5.20 Structure of Timer 1 .............................................................................................. 3-108

Fig. 3.5.21 Structure of One-shot start register ..................................................................... 3-109

Fig. 3.5.22 Structure of Timer X mode register .................................................................... 3-110

Fig. 3.5.23 Structure of Prescaler X ....................................................................................... 3-111

Fig. 3.5.24 Structure of Timer X .............................................................................................. 3-111

Fig. 3.5.25 Structure of Timer count source set register ..................................................... 3-112

Fig. 3.5.26 Structure of Serial I/O2 control register .............................................................. 3-113

Fig. 3.5.27 Structure of Serial I/O2 register ........................................................................... 3-113

Fig. 3.5.28 Structure of A/D control register .......................................................................... 3-114

Fig. 3.5.29 Structure of A/D conversion register (low-order) ............................................... 3-114

Fig. 3.5.30 Structure of A/D conversion register (high-order) ............................................. 3-115

Fig. 3.5.31 Structure of MISRG ............................................................................................... 3-115

Fig. 3.5.32 Structure of Watchdog timer control register ..................................................... 3-116

Fig. 3.5.33 Structure of Interrupt edge selection register .................................................... 3-116

Fig. 3.5.34 Structure of CPU mode register .......................................................................... 3-117

Fig. 3.5.35 Structure of Interrupt request register 1 ............................................................. 3-118

Fig. 3.5.36 Structure of Interrupt request register 2 ............................................................. 3-118

Fig. 3.5.37 Structure of Interrupt control register 1 .............................................................. 3-119

Fig. 3.5.38 Structure of Interrupt control register 2 .............................................................. 3-119

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