SH7713 datasheet(131/904 Pages) RENESAS

131 / 904 page

Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 91 of 860

REJ09B0288-0150

Table 3.8

Extended Repeat Control Instructions

Instruction

Operation

Number of Execution

States

LDRS @(disp,PC)

Calculates (disp x 2 + PC) and stores the result to

the RS register

LDRE @(disp,PC)

Calculates (disp x 2 + PC) and stores the result to

the RE register

LDRC #imm

Sets 8-bit immediate data imm to the RC[11:0] bits

of the SR register and sets the information related

to the number of repetitions to the RF[1:0] bits of

the SR.

RC[11:0] can be specified as 0 to 255.

During extended repeat control, bit 0 of the RE

LDRC Rm

Sets the[11:0] bits of the Rm register to the

RC[11:0] bits of the SR register and sets the

information related to the number of repetitions to

the RF[1:0] bits of the SR. RC[11:0] can be

specified as 0 to 4095.

During extended repeat control, bit 0 of the RE

By executing the LDRC instruction, the CPU performs the extended repeat control function. To

indicate that the CPU is being in extended repeat control, bit 0 of the RE register is set to 1 by

executing the LDRC instruction. To change the RE register value by a process such as an

exception handling, bit 0 of the RE register must be saved and restored correctly. By saving and

restoring the RC[11:0] bits, DSP bit, and RF[1:0] bits of the SR register, RE register, and RS

such as exception handling.

Restrictions on Extended Repeat Loop Control

1. Extended repeat control instruction assignment

The LDRC instruction must be executed after executing the LDRS and LDRE instructions. In

addition, note that at least one instruction is required between the LDRC instruction and a

repeat start instruction.

2. Illegal instruction one or more instructions following the repeat detection instruction

If one of the following instructions is executed as a repeat end instruction, an illegal instruction

exception occurs.

 Branch instructions

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