SH7713 datasheet(135/904 Pages) RENESAS

135 / 904 page

Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 95 of 860

REJ09B0288-0150

Double data transfer instructions can be described in parallel to the DSP operation instructions.

Even if a conditional operation instruction is specified in parallel to a double data transfer

instruction, the specified condition does not affect the data transfer operations. For details, refer to

section 3.5, DSP Data Operation Instructions.

Double data transfer instructions can access only the X memory or Y memory and cannot access

other memory space. The X bus and Y bus are 16 bits and support 64-byte address spaces

corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF,

respectively. Because these areas are included in the P2/Uxy area, they are not affected by the

cache and address translation unit.

Single Data Transfer Instructions: The single data transfer instructions access any memory

location. All DSP registers other than the DSR* can be specified as source and destination

operands. Guard bit registers A0G and A1G can also be specified as two independent registers.

Because these instructions use the L bus (LAB and LDB), these instructions can access any logical

space handled by the CPU. If these instructions access the cacheable area while the cache is

enabled, the area accessed by these instructions are cached. The X memory and Y memory are

mapped to the logical address space and can also be accessed by the single data transfer

instructions. In this case, bus conflict may occur between data transfer and instruction fetch

because the CPU also uses the L bus for instruction fetches.

The single data transfer instructions can handle both word and longword data. In word data

transfer, only the upper word of the operand register is valid. In word data load, word data is

loaded into the upper word of the destination registers and the lower word of the destination is

automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage.

In longword data load, longword data is loaded into the upper and lower word of the destination

LDB bus.

Notes: * Because the DSR register is defined as the system register, it can be accessed by the

LDS or STS instruction.

1. Any data transfer instruction is executed at the MA stage of the pipeline.

2. Any data transfer instruction does not modify the condition code bits of the DSR

System Control Instructions: The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can

also be used as the CPU system registers. Accordingly, data transfer operations between these

DSP system registers and general registers or memory can be executed by the STS and LDS

instructions. These DSP system registers can be treated as the CPU system register such as PR,

MACL and MACH and can use the same addressing modes.

SH7713 Datasheet(PDF) 135 Page - Renesas Technology Corp