SH7713 datasheet(149/904 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 109 of 860

REJ09B0288-0150

Table 3.16

DSR Register Bits

Bits

Bit Name

Initial

Value

R/W

Function

31 to

—

All 0

Reserved Bits

These bits are always read as 0. The write value

should always be 0.

11 to 9 TS2 to TS0 All 0

R/W

T Bit Status Selection

Specifies the operation result status to be set in the T

bit in the SR register if the TC bit is 1. If the S bit of

the SR register is set to 1, an overflow is detected.

000: Carry/borrow mode

001: Negative value mode

010: Zero mode

011: Overflow mode

100: Signed greater mode

101: Signed greater than or equal to mode

110: Reserved (setting prohibited)

111: Reserved (setting prohibited)

R/W

TC Bit

0: The T bit of the SR register is not affected by the

DSP instruction.

1: The T bit of the SR register changes according to

the TS bit of the DSR register while the DSP

instruction is executed. Note, however, the T bit

does not change during conditional DSP instruction

execution.

R/W

Signed Greater Bit

Indicates that the operation result is positive (except

0), or that operand 1 is greater than operand 2

1: Operation result is positive, or operand 1 is greater

than operand 2

R/W

Zero Bit

Indicates that the operation result is zero (0), or that

operand 1 is equal to operand 2

1: Operation result is zero (0), or operands are equal

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