ATA5428-PLSW datasheet(29/100 Pages) ATMEL

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4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

4.1

Pin CLK

Pin CLK is an output to clock a connected microcontroller. The clock frequency f

CLK is calculated

as follows:

Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. The

signal at CLK output has a nominal 50% duty cycle.

Figure 4-3.

Clock Timing

4.2

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As shown in Figure 4-2

on page 27, this clock cycle T

DCLK is derived from the crystal oscillator (XTO) in combination with

a divider.

DCLK controls the following application relevant parameters:

• Timing of the polling circuit including bit check

• TX bit rate

The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range

(BR_Range) which is defined in control register 6 (see Table 7-20 on page 42) and XLim which

is defined in control register 4 (see Table 7-13 on page 40). This clock cycle T

XDCLK is defined by

the following formulas for further reference:

BR_Range

⇒

BR_Range 0: T

XDCLK = 8 × TDCLK × XLim

BR_Range 1: T

XDCLK = 4 × TDCLK × XLim

BR_Range 2: T

XDCLK = 2 × TDCLK × XLim

BR_Range 3: T

XDCLK = 1 × TDCLK × XLim

CLK

XTO

-----------

CLK_ON

(Control register 3)

N_RESET

CLK

VSOUT

Thres_2 = 2.38V (typically)

Thres_1 = 2.3V (typically)

DCLK

XTO

-----------

ATA5428-PLSW Datasheet(PDF) 29 Page - ATMEL Corporation

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